With more and more transistors being placed on a chip to increase the number of functions, the number of input/output (I/O) pads per integrated circuit chip has increased significantly. The increase in the number of I/o pads per chip are making traditional bonding methods, such as wire bonding (WB) and tape automated bonding (TAB) difficult. Flip chip attach (FCA), which is usually an area array in contrast to a peripheral array for WB and TAB, is becoming increasingly pervasive due to the number of pads. In FCA, the chip is bumped with a lead-rich Pb/Sn alloy ball using metal deposition through a resist-mask, for example. The bonding of this chip is achieved by self alignment and placing the chip on the substrate which has been covered with high viscosity flux to reduce oxides. The chip is held in place by the flux. The whole assembly (chip and substrate) is subsequently heated in the range from 350 to 400.degree. C. to a temperature which melts the solder forming an interconnect between balls or bumps on a chip and respective pads on a substrate.
Conventionally the substrates were multi-layer ceramic (MLC) structures that could withstand temperatures up to 400.degree. C. Dictated by both the number of pads and lower cost, there is a growing need to attach similar C4 bumped integrated circuit chips to organic substrates made of polymer/filler composites, such as FR4. Such organic substrates degrade at solder reflow temperatures above 300.degree. C. Thus a low temperature joining material is needed to attach the C4 bumps of a chip to respective substrate pads.
One method to attach electrodes such as C4 bumped chips to an organic substrate is by capping the C4 bumps first with a low temperature melting Pb/Sn-eutectic solder such as described in U.S. Ser. No. 08/710992 filed Sep. 25, 1996 by Berger et al. entitled "Method for Making Interconnect for Low Temperature Chip Attachment" (YO996073) and assigned to the assignee herein. The Pb/Sn solder cap over the C4 bump may be accomplished by vapor depositing the metal components through a resist mask, followed by solder reflow step. The masking process requires expensive alignment and lithographic steps, and the vapor deposition process is costly due to high vacuum processing. The bonding is accomplished by reflowing the Pb/Sn-eutectic solder at temperatures below 250.degree. C. using acidic flux. Subsequently, the flux is removed using organic solvents that may be chloro-fluoro-carbon (CFC) based.